Example 3: Parameterization Of Logic Diagram - BONFIGLIOLI AGILE Applications Manual

6.5

Example 3: Parameterization of logic diagram

Inverter Release
VTable
Function Table: Input Buffer
FT-input buffer
1362
Function Table
FT-instruction
1343
FT-input 1
1344
FT-input 2
1345
FT-input 3
1346
FT-input 4
1347
FT-output 1
1350
FT-output 1
1351
VPlus
Op. Mode Digital Output 1
142
142
OR
Index 1
S2IND
S3IND 1
S4IND
S5IND
530 = 80 - FT-Output Buffer 1
AND
Index 2
&
Index 1 Index 2 Index 3
70 - 71 - 72 -
Inverter Release S2IND S3IND
Index 1
2 - OR
2002
2003
VPLC / PLC
VPLC / PLC
XOR 1
Index 3
S1OUT
=1
Index 4 Index 5
73 - 74 -
S4IND S5IND
Index 2 Index 3
1 - AND 3 - XOR 1
2001 2102
2101 2004
2005
2401
08/10
08/10