70,71,72] Monoflop (Non-Retriggerable), Superior - BONFIGLIOLI AGILE Applications Manual

4.6.3

[70,71,72] Monoflop (non-retriggerable), Superior

Type
I1 b M, Monoflop edge 1
I2 b M ¯ , Monoflop edge 2
b Superior Set input
I3
I4 b Superior Reset input
70 [ms], 71 [s] or 72 [min]
Description:
Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at
input 2. The time set in P1 is the On-Time (High) and the time set in P2 is the ignore edge time
(Low). The set on-time starts again with each edge.
TRUE at the Superior Set input sets the output to TRUE. TRUE at the Superior Reset input sets
the output to FALSE.
Via the output buffer, the output signal is globally available.
Inputs Superior Set and Superior Reset are connected in series with the function. Levels on
Monoflop inputs I1 and I2 As soon as the Superior Set or Superior Reset is reset, the output is
switched to the internally saved value.
08/10
08/10
Function Type
O1 b
O2 b
t
P1
P2 t
Monoflop (non-retriggerable), Superior
I1
M
0
P1 P2
(on-time) (ignore edge time)
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 =
On-time (High)
ignore edge time
I2 I3 I4 O1
M ¯ SS SR Q
x x x 1 0
x x 1 0 1
1 x 0 0
x 0 1 0 0
O 1
State
Off (Superior)
On (Superior)
Pulse
Pulse
67
67