30] D-Flip-Flop, Superior - BONFIGLIOLI AGILE Applications Manual

4.4.5

[30] D-Flip-Flop, Superior

Type
b C, Clock
I1
I2 b D, Data input
I3 b Superior Set input
b Superior Reset input
I4
Description:
If a positive edge is received at input 1 (clock pulse input C, Clock) the signal is transferred
from signal input 2 (data input D) to the output.
TRUE at the Superior Set input sets the output to TRUE. TRUE at the Superior Reset input sets
the output to FALSE.
Via the output buffer, the output signal is globally available.
Inputs Superior Set and Superior Reset are connected in series with the function. Levels on C
input I1 and D input I2 are processed internally. As soon as the Superior Set or Superior Reset
is reset, the output is switched to the internally saved value.
56
56
Function Type
b
O1
O2 b
P1
P2
D-Flip-Flop, Superior
C
x
x
x
0
0
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 = O
O1
State
D SS SR Q
x x 1 0 Off (Superior)
x 1 0 1 On (Superior)
x 0 0 Q Hold
n-1
1 0 0 0 0 Sample
1 1 0 0 1 Sample
1
08/10
08/10