140,141,142] Delay (Retriggerable), Master - BONFIGLIOLI AGILE Applications Manual

4.5.2

[140,141,142] Delay (retriggerable), Master

Typ
e
b F, edge
I1
I2
I3 b Master Set input
I4 b Master Reset input
140 [ms], 141 [s] or 142 [min]
Description:
The positive edge at input 1 is transferred to the output after delay t1 (P1), the negative edge
after delay t2 (P2). The delay time starts again with each edge.
TRUE at the Master Set input sets the output to TRUE. TRUE at the Master Reset input sets the
output to FALSE.
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
(positive delay)
62
62
Function Type
b
O1
O2 b
P1 t
P2 t
Delay (retriggerable), Master
F
x
x
0
1
P1 P2
(negative delay)
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 =
On delay t1
Off delay t2
O1
State
MS MR Q
x 1 0 Off (Master)
1 0 1 On (Master)
1 0 0 On delay t1
t1
0 0 0 Off delay t2
t2
O 1
08/10
08/10