130] D-Flip-Flop, Master - BONFIGLIOLI AGILE Applications Manual

4.4.6

[130] D-Flip-Flop, Master

Type
I1 b C, Clock
b D, Data input
I2
b Master Set input
I3
I4 b Master Reset input
Description:
If a positive edge is received at input 1 (clock pulse input C, Clock) the signal is transferred
from signal input 2 (data input D) to the output.
TRUE at the Master Set input sets the output to TRUE. TRUE at the Master Reset input sets the
output to FALSE.
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
08/10
08/10
Function Type
O1 b
b
O2
P1
P2
D-Flip-Flop, Master
C
x
x
x
0 1
0 1
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 = O 1
O1
State
D MS MR Q
x x 1 0 Off (Master)
x 1 0 1 On (Master)
x 0 0 Q Hold
n-1
0 0 0 0 Sample
1 0 0 1 Sample
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