BONFIGLIOLI AGILE Applications Manual page 153

The following diagram is obtained for the signals of the function table:
2003=1
5a
2404
In the first step, the states and transitions are translated into instructions.
Setting state outputs:
The easiest way to set a digital signal (independent of one or several input signals) is using a
Boolean operation. In this application, an OR instruction is used and an input is set to TRUE. In
FT target output 1
this way,
FALSE (=0).
2
2402=0
2411=1
For states 3 to 5, instructions can be created in the same way.
Clock generator (state 3a)
3a
2403
The clock generator of state 5a is created in the same way as 3a.
08/10
08/10
4
2401=0
2410=1
2004=1
2004=1
5
2006=1
2402 = 1
("2005=0")
2410 = 0
1350 is set to TRUE (=1) and
FT-Instruction
1343
FT input 1
1344
FT input 2
1345
FT input 3
1346
FT input 4
1347
FT-Parameter 1
1348
FT-Parameter 2
1349
FT target output 1
1350
FT target output 2
1351
FT instruction
1343
FT input 1
1344
FT input 2
1345
FT input 3
1346
FT input 4
1347
FT-Parameter 1
1348
FT-Parameter 2
1349
FT-Target Output 1
1350
FT-Target Output 2
1351
VPLC / PLC
VPLC / PLC
2005=1 3
2401=1
2411=0
2002=1
1
2002=1
No
Initiator
2
2402=0
2411=1
FT target output 2
2 – OR
6 – TRUE
7 – FALSE
7 – FALSE
7 – FALSE
0
0
2411 FT-Output buffer 11
2402 FT-Output buffer 2
80 – Clock generator
2003 - Input buffer 3
7 – FALSE
7 – FALSE
7 – FALSE
100
100
0
0
3a
2403
2003=1
1351 is set to
151
151