110] Rs-Flip-Flop, Master - BONFIGLIOLI AGILE Applications Manual

4.4.2

[110] RS-Flip-Flop, Master

Type
I1 b Set input
b Reset input
I2
b Master Set input
I3
I4 b Master Reset input
Description:
The inputs of the instruction are the assigned signal sources.
TRUE at the Set input sets the output to TRUE. TRUE at the Reset input sets the output to
FALSE. If FALSE is present on both inputs, the current status of the output signal is maintained.
TRUE at the Master Set input sets the output to TRUE. TRUE at the Master Reset input sets the
output to FALSE.
Priority:
Master Reset (highest priority)
Master Set
Reset
Set (lowest priority)
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
Set:
Save:
Reset:
Off:
Master-Set:
Master-Reset:
08/10
08/10
Function Type
O1 b
b
O2
P1
P2
RS-Flip-Flop, Master
S
x
X
0
0
1
1
TRUE at the S input sets the output to TRUE.
If all inputs are FALSE, the output remains unchanged.
If R input is TRUE, the output is set to logic FALSE.
If both inputs are set to TRUE, the output is FALSE.
MS, set output to TRUE.
MR, set output to FALSE (CLR).
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 = O 1
O1
State
R MS MR Q
x X 1 0 Off (Master)
X 1 0 1 On (Master)
0 0 0 Q Hold
n-1
1 0 0 0 Reset
0 0 0 1 Set
1 0 0 0 Off
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