50,51,52] Delay (Non-Retriggerable), Superior - BONFIGLIOLI AGILE Applications Manual

4.5.3

[50,51,52] Delay (non-retriggerable), Superior

Type
b F, edge
I1
I2
I3 b Superior Set input
b Superior Reset input
I4
50 [ms], 51 [s] or 52 [min]
Description:
The positive edge at input 1 is transferred to the output after delay t1 (P1), the negative edge
after delay t2 (P2). The delay time starts again with each edge.
TRUE at the Superior Set input sets the output to TRUE. TRUE at the Superior Reset input sets
the output to FALSE.
Via the output buffer, the output signal is globally available.
Inputs Superior Set and Superior Reset are connected in series with the function. Levels at in-
put I1 are processed internally. As soon as the Superior Set or Superior Reset is reset, the out-
put is switched to the internally saved value.
Digital
Input
(positive delay)
08/10
08/10
Function
O1
O2
P1
P2
Delay (non-retriggerable), Superior
Signal Function &
source output
P1 P1
(negative delay)
Type Function
b output O1
b
negated output O2 =
t On delay t1
t
Off delay t2
Logic table
O1
State
F SS SR Q
x x 1 0 Off (Superior)
x 1 0 1 On (Superior)
0 1 0 0 On delay t1
t1
1 0 0 0 Off delay t2
t2
VPLC / PLC
VPLC / PLC
O 1
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