211] Bit Arithmetical Shift Right; 212] Bit Shift Left - BONFIGLIOLI AGILE Applications Manual

Master Set sets all bits of the output value (Output = 0xFFFF).
Master Reset deletes all bits of the output value (Output = 0x0000).
Example
1) 1: One shift
2) 4: Four shifts
3) 8: Eight shifts
In example 1):

5.11.6 [211] Bit arithmetical shift right

Type
I1 % input value 1
I2 - -
b Master Set
I3
I4 b Master Reset
Description:
The input value at I1 is shifted to the right bitwise by the number of shifts (P2). The most sig-
nificant bit (sign bit) is maintained.
Master Set sets all bits of the output value (Output = 0xFFFF).
Master Reset deletes all bits of the output value (Output = 0x0000).
Example
1) 1: One shift
2) 4: Four shifts
3) 8: Eight shifts
In example 1):

5.11.7 [212] Bit shift left

Type
% input value 1
I1
I2 - -
b Master Set
I3
b Master Reset
I4
Description:
The input value at I1 is shifted to the left bitwise by the number of shifts (P2). Right side is
filled with zeroes.
Master Set sets all bits of the output value (Output = 0xFFFF).
Master Reset deletes all bits of the output value (Output = 0x0000).
130
130
P2 I1
0xF00F
0x00FF
0xFF00
Function Type
O1 %
O2 %
-
P1
P2 i
P2
0xF00F
0x00FF
0xFF00
Function Type
%
O1
O2 %
-
P1
i
P2
VPLC / PLC
O1 O2
0x7807 0x87F8
0x000F 0xFFF0
0x00FF 0xFF00
Function
I1 bitwise shifted by P2, sign
bit is maintained
inverted output
-
Number of shifts
I1 O1 O2
0xF807 0x07F8
0x000F 0xFFF0
0xFFFF 0x0000
Function
I1 bitwise shifted by P2
inverted output
-
Number of shifts
VPLC / PLC
08/10
08/10