170,171,172] Monoflop (Non-Retriggerable), Master - BONFIGLIOLI AGILE Applications Manual

4.6.4

[170,171,172] Monoflop (non-retriggerable), Master

Type
I1 b M, Monoflop edge 1
I2 b M ¯ , Monoflop edge 2
I3 b Master Set input
I4 b Master Reset input
170 [ms], 171 [s] or 172 [min]
Description:
Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at
input 2. The time set in P1 is the On-Time (High) and the time set in P2 is the ignore edge time
(Low). The set on-time starts again with each edge.
TRUE at the Master Set input sets the output to TRUE. TRUE at the Master Reset input sets the
output to FALSE.
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
68
68
Function Type
O1 b
O2 b
P1 t
P2 t
Monoflop (non-retriggerable), Master
I1
M
0
P1 P2
(on-time) (ignore edge time)
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 = O
On-time (High)
ignore edge time
I2 I3 I4 O1
M ¯ MS MR Q
x x x 1 0
x x 1 0 1
1 x 0 0
x 1 0 0 0
1
State
Off (Master)
On (Master)
Pulse
Pulse
08/10
08/10