180,181,182] Clock Generator, Master - BONFIGLIOLI AGILE Applications Manual

4.6.6

[180,181,182] Clock generator, Master

Type
I1 b S clock generator 1
b S ¯ Clock generator 2
I2
I3 b Master Set input
I4 b Master Reset input
180 [ms], 181 [s] or 182 [min]
Description:
As long as input 1 is TRUE and input 2 is FALSE, the set pulse pattern is output. The pulse pat-
tern at the output always starts with TRUE. The clock pattern is defined by the on-time and the
off-time. The time set in P1 is the on-time (High) and the time set in P2 is the off-time (Low).
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
70
70
Function Type
O1 b
b
O2
P1 t
P2 t
Clock generator, Master
S
x
x
x
0
1
1
P1 P2
(on-time) (off-time)
VPLC / PLC
VPLC / PLC
Function
output O1
negated output O2 = O 1
On-time (High)
Off time (Low)
O1
State
S ¯ MS MR Q
x x 1 0 Off (Master)
X 1 0 1 On (Master)
1 0 0 0 Off
x 0 0 0 Off
0 0 0 t1 1 Clock On
0 0 0 t2 0 Clock Off
08/10
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