9 THEORY OF OPERATION
that sample their binary DC input voltages for analog level at the same high sampling rate as they do for analog signal
inputs provide great analysis tools: they include all the measured and derived instantaneous signals in their oscillography
records (COMTRADE files). This includes flags driving transmission, received DC voltage, local AC currents, and all rele-
vant instantaneous signals leading towards the trip/no-trip condition. Having four receive channels, it is even possible to
loop back the transmit voltages to monitor both the signal connected to a local carrier equipment, and received at the
After all the local and remote pulses are aligned and conditioned, a coincidence condition X is established as per the num-
ber of terminals and type of the scheme (tripping vs. blocking). For example, for a three-terminal permissive scheme the
X = FDH AND LOC AND REM1 AND REM2
The above logic is executed for the positive polarity in single-comparison schemes, and independently for positive and neg-
ative polarities in dual-comparison schemes.
The coincidence condition is driving an explicitly implemented integrator (summator). In the L60, the integrator counts up by
10 units if the coincidence input is logic 1, counts down by 5 counts if the coincidence input is momentarily logic 0, and
counts down by 20 if the input is in logic 0 for extended periods of time. This provides extra security for chattering inputs,
allowing for eventual trips in clear situations, and provides for full reset of the integrator before the next coincidence period.
The output of the integrator (or two integrators in dual-comparison schemes) is compared with the coincidence timer setting
yielding the final trip/no-trip flag.
The following figure shows an example of the coincidence integration for an internal fault as recorded in a COMTRADE file
by the relay under test.
87PC BKR1 CURRENT
POS INT INPUT
87PC POS INTEGRATOR
Figure 9–27: TRIP INTEGRATION LOGIC (RELAY COMTRADE RECORD)
The L60 can be programmed to perform an automatic checkback. Under normal system conditions, a relay could initiate
transmission and modulate the analog signal to exchange small amounts of information. The ability to abort in cases of sys-
tem faults is a key to successful deployment. This feature could replace the guard signal when the latter is not available.
Furthermore, it provides a more comprehensive communications check from one center of relaying intelligence in the
microprocessor at one end to its companion at the other line terminal. This covers all links in the chain of communications,
not just the carrier part of the system.
The advantages of the L60 implementation of phase comparison relaying with more pure and secure digital calculations are
summarized below. The following methods are critically important to the effectiveness of the new 87PC element.
Separated CT inputs from multiple breakers feeding the line enables proper handling of bus through faults at a line ter-
minal as explained above.
Developing comparison signals from each breaker separately, and combining with the logic explained above, elimi-
nates security risks caused by combining the breaker currents before calculating the comparison signals.
L60 Line Phase Comparison System
1) Internal AG fault
2) Internal BG fault during
3) Composite signal
4) Local positive pulses
5) Received positive pulses
6) Integrator input
7) Integrator output
8) 87PC operation