Flashing yellow — internal mode while receiving a valid data packet
Solid red — (switch to) internal timing mode while not receiving a valid data packet
The link/activity LED status is as follows:
Flashing green — FPGA is receiving a valid data packet
Solid yellow — FPGA is receiving a "yellow bit" and remains yellow for each "yellow bit"
Solid red — FPGA is not receiving a valid packet or the packet received is invalid
3.3 DIRECT INPUT AND OUTPUT COMMUNICATIONS
L60 Line Phase Comparison System