GE L60 Instruction Manual page 93

Line phase comparison system, ur series
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3 HARDWARE
Modules shipped from January 2012 have status LEDs that indicate the status of the DIP switches, as shown in the follow-
ing figure.
The clock configuration LED status is as follows:
Flashing green — loop timing mode while receiving a valid data packet
Flashing yellow — internal mode while receiving a valid data packet
Solid red — (switch to) internal timing mode while not receiving a valid data packet
The link/activity LED status is as follows:
Flashing green — FPGA is receiving a valid data packet
Solid yellow — FPGA is receiving a "yellow bit" and remains yellow for each "yellow bit"
Solid red — FPGA is not receiving a valid packet or the packet received is invalid
GE Multilin
3.3 DIRECT INPUT AND OUTPUT COMMUNICATIONS
Figure 3–44: STATUS LEDS
L60 Line Phase Comparison System
3
3-41

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