Mitsubishi Electric MELSEC iQ-R Series Programming Manual page 906

Processing details
• These instructions perform addition of the data stored in the devices specified by (s) to (s)+(n)-1 and calculate the
horizontal parity, and stores the added data in the device specified by (d) and the horizontal parity in the device specified by
(d)+1. The 16-bit conversion mode and 8-bit conversion mode are available for these instructions. The conversion mode
can be selected by turning on or off SM772.
• If the value specified in (n) is 0, no processing is performed.
• If an overflow occurs in the calculated result stored in (d), the following operations are performed. SM700 does not turn on.
32767+2=-32767
(7FFFH+0002H=8001H)
• These instructions calculate the horizontal parity value and sum check value as the error check methods used in
communications. There is another check method called CRC (cyclic redundancy check) in addition to the CCD(P)
instruction. (Page 944 CRC(P))
• The operation in each conversion mode is described below.
■16-bit conversion mode (while SM772 is OFF)
With regard to (n) data points starting from (s), the addition data and horizontal parity data of upper 8 bits and lower 8 bits are
stored to (d) and (d)+1 respectively.
Ex.
When (n)=6
<Calculation of addition data value>
In 16-bit conversion mode, addition data is determined by adding 6 bytes in the following shaded portion. The addition data is
thus determined as "0315H", and therefore "0315H" is stored in the device specified by (d).
Decimal
D0 24932
D1 4219
D2 -1333
D3 -1
D4 32761
D5 10000
<Calculation of horizontal parity value>
In 16-bit conversion mode, the above shaded portion becomes the horizontal parity calculation target.
The number of ON (1) bits is calculated to determine the parity value which becomes ON (1) when the number of ON (1) bits
is finally odd or OFF (0) when it is finally even. The horizontal parity value is stored in the device specified by (d)+1.
In the following table, 5FH is stored in the device specified by (d)+1.
Bit/horizontal parity value
Upper 8 bits of D0
Lower 8 bits of D0
Upper 8 bits of D1
Lower 8 bits of D1
Upper 8 bits of D2
Lower 8 bits of D2
Horizontal parity value
7 APPLICATION INSTRUCTIONS
904
7.19 Check Code Instructions
Hexadecimal
Upper Lower
61H 61H 61H 64H 64H 64H
10H 10H 10H 7BH 7BH 7BH
FAH FAH FAH CBH CBH CBH
FFH FFH
7FH F9H
27H 10H
b7 b6
0 1
0 1
0 0
0 1
1 1
1 1
0 1
-32767+-2=32767
(8001H+FFFEH=7FFFH)
b5 b4 b3
1 0 0
1 0 0
0 1 0
1 1 1
1 1 1
0 0 1
0 1 1
b2 b1 b0
0 0 1
1 0 0
0 0 0
0 1 1
0 1 0
0 1 1
1 1 1
Value
61H
64H
10H
7BH
FAH
CBH
5FH