Mitsubishi Electric MELSEC iQ-R Series Programming Manual page 501

■Applicable devices
Operand Bit
X, Y, M, L, J\
SM, F, B, SB,
FX, FY
*1
(s)  
*1
 
(n1)
*1
(n2)  
*1
 
(d)
*1
(n3)  
*1 FX and FY cannot be used.
Processing details
• When SM773 is OFF, the contents of (s) and (d) are converted to 4-digit BCD (0000 to 9999). After the data in lower (n2)
digits from the (n1)th digit is transferred (combined) to (d) starting from the (n3)th digit, the data is converted into BIN and
then stored in (d).
In the case of (n1) = 4, (n2 )= 2 and (n3) = 3
4th digit 3rd digit 2nd digit
3 2 1
10 10 10
3 2 1
10 10 10
• When SM773 is on, conversion from BIN to BCD is not performed and data are shifted in units of 4 bits.
In the case of (n1) = 4, (n2 )= 2 and (n3) = 3
4th digit 3rd digit 2nd digit
• When digit specification of bit is used for (n1), the number of digits becomes the specified number of digits  4 bits from the
start bit device.
Ex.
To specify "3 digits  4 bits" from X0:
[ SMOV K3X0 K 3
(1) (2)
(1) Specified constant
(2) Start bit device
3rd digit
X14 X13 X12 X11 X10 XF XE XD XC XB XA X9 X8 X7 X6 X5 X4 X3 X2 X1 X0
Digit specification denotes the "specified number of digits 34 bits" = 12 bits from the start bit device X0.
Word
T, ST, C, D, W, U\G, J\,
SD, SW, FD, R, U3E\(H)G
ZR, RD
 
 
 
 
 
1st digit
(s) (16-bit binary data)
1.
(s)' (BCD 4-digit data)
0
10
2.
(d)' (BCD 4-digit data)
0
10
3.
(d) (16-bit binary data)
1st digit
(s) (16-bit binary data)
1.
(d) (16-bit binary data)
K2 K2X100 K2
2nd digit 1st digit
Double word Indirect
Z LT, LST, LZ
LC
  
  
  
  
  
1.
Conversion
(s) is converted from binary to BCD data.
2.
Shifting
Lower (n2) digits starting from the (n1)th digit are
transferred (combined) to (d)' starting from the (n3)th digit.
In the case of this example, the first and fourth digits of (d)'
are not affected even if data is transferred from (s)'.
3.
Conversion
The combined data (BCD) is converted into binary, and
stored to (d).
1.
Shifting data in units of 4 bits
Lower (n2)4-bit data from (n1)4th bit is transferred
(combined) by lower (n2)4-bit data from (n3)4th bit of
(d). In the case of this example, the first and fourth digits of
(d) are not affected even if data is transferred from (s).
]
Constant Others
specification
K, H E $
    
    
    
    
    
6 BASIC INSTRUCTIONS
6.7 Data Transfer Instructions
6
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