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3.3.1.5
Static Memory Control Register 0 (MSC0)
The table below shows how to program both nCS0 (synchronous flash memory on the Intel
PXA270 Processor) and nCS1 (asynchronous flash memory on the main board) for asynchronous
read accesses. The setting for nCS0 is optimized for CLK_MEM = 130 MHz, but it also works
with CLK_MEM = 91 MHz. The setting for nCS1 is optimized for CLK_MEM = 91 MHz.
Upon reset or power-up, the MEM_CLK frequency defaults to 91 MHz, so that the main board
flash memory is available for booting if main board switch SW2 is set to the NO-DOT position.
MSC0 Recommended Settings:
7
F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
X
XXX
XXXX
0
011
1001
1,3
1,3
1,3
NOTES:
1. These values are based upon the main board switch SW2 (SWAP_FLASH) being set to DOT (nCS0 = Intel
flash). If SWAP_FLASH is set to NO-DOT (nCS0 = main board flash), then the upper and lower halves of this register must be
swapped.
To determine the state of SWAP_FLASH, software must use the procedure described in
Configuration Register (see
2. This value must agree with main board switch SW1 (flash-memory bus width). See
PXA27x Processor Developer's Kit Main Board" on page
3. Values are for MEM_CLK = 91-MHz.
4. Values are for MEM_CLK = 130-MHz.
®
5. Even though the Intel
PXA270 Processor flash is synchronous, writes are performed asynchronously. Thus, these values are
required. These values are ignored for reads (with the exception of bit 3 or 19, depending on SW2) once the Synchronous Static
Memory Configuration Register (SXCNFG; see
®
Intel
PXA27x Processor Developer's Kit - User's Guide
F
0
Stand-alone Intel
XXXX
X
XXX
Processor card with main board
1111
0
010
1,2,
1,3
1,3
3
Table
16).
Section
3.3.1.9) has been configured.
B
8
®
PXA270 Processor
1
010
0111
1
010
0111
Notes
1,4,
1,4,5
1,4,5
5
Table 3, "Switches and Settings, Intel®
32for more information.
F
8
7
6
5
4
3
2
1010
0
1010
0
1,4,
1,4,5
5
®
PXA270 Processor
Section 3.2.1
to access the System
®
2
1
0
011
011
1,4,5
73
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