Sdac2 Mode Register; Sdac2 Ch.n Data Register; Sdac2 Interrupt Flag Register - Epson Arm S1C31 Series Technical Manual

22 HW Processor (HWP) and Sound Output (SDAC2)
Bit 2 Reserved
Bit 1 RESAMPEN
This bit enables the resampler.
1 (R/W): Enable resampler
0 (R/W): Disable resampler
Bit 0 SDACEN
This bit enables the SDAC operations.
1 (R/W): Enable SDAC operations (The operating clock is supplied.)
0 (R/W): Disable SDAC operations (The operating clock is stopped.)

SDAC2 Mode Register

Register name Bit
SDAC2MOD 15–9 –
8
7–2 –
1–0 PWMMODE[1:0]
Bits 15–9 Reserved
Bit 8 PWMOUTEN
This bit enables the SDAC2 output pins to output the PWM signals.
1 (R/W): Enable PWM signal output
0 (R/W): Disable PWM signal output
Bits 7–2 Reserved
Bits 1–0 PWMMODE[1:0]
These bits set th SDAC2 operating mode.
SDAC2MOD.PWMMODE[1:0] bits

SDAC2 Ch.n Data Register

Register name Bit
SDAC2_nDAT 15–10 –
9–0 DAT[9:0]
Bits 15–10 Reserved
Bits 9–0 DAT[9:0]
These bits store sound data.
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).

SDAC2 Interrupt Flag Register

Register name Bit
SDAC2INTF 15–8 –
7–4 –
3
2
1
0
Bits 15–4 Reserved
22-30
Bit name Initial
0x00
PWMOUTEN 0
0x00
0x00
Table 22.7.2 SDAC2 Operating Mode
0x3
0x2
0x1
0x0
Bit name Initial
0x00
0x000
Bit name Initial
0x00
0x0
ERR1IF 0
DATREQ1IF 0
ERR0IF 0
DATREQ0IF 0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
H0 R
H0 R/W
Mode
CPLM mode 2
CPLM mode 1
Normal mode
Buzzer mode
Reset R/W
– R –
H0 R/W
Reset R/W
– R –
– R
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
H0 R/W
S1C31D41 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.1)