I2C Ch.n Interrupt Enable Register - Epson S1C31W65 Technical Manual

The following shows the correspondence between the bit and interrupt:
I2C_nINTF.BYTEENDIF bit: End of transfer interrupt
I2C_nINTF.GCIF bit:
I2C_nINTF.NACKIF bit:
I2C_nINTF.STOPIF bit:
I2C_nINTF.STARTIF bit:
I2C_nINTF.ERRIF bit:
I2C_nINTF.RBFIF bit:
I2C_nINTF.TBEIF bit:

I2C Ch.n Interrupt Enable Register

Register name Bit
I2C_nINTE 15–8 –
7
6
5
4
3
2
1
0
Bits 15–8 Reserved
Bit 7 BYTEENDIE
Bit 6 GCIE
Bit 5 NACKIE
Bit 4 STOPIE
Bit 3 STARTIE
Bit 2 ERRIE
Bit 1 RBFIE
Bit 0 TBEIE
These bits enable I2C interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
I2C_nINTE.BYTEENDIE bit: End of transfer interrupt
I2C_nINTE.GCIE bit:
I2C_nINTE.NACKIE bit:
I2C_nINTE.STOPIE bit:
I2C_nINTE.STARTIE bit:
I2C_nINTE.ERRIE bit:
I2C_nINTE.RBFIE bit:
I2C_nINTE.TBEIE bit:
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
General call address reception interrupt
NACK reception interrupt
STOP condition interrupt
START condition interrupt
Error detection interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name Initial
0x00
BYTEENDIE 0
GCIE 0
NACKIE 0
STOPIE 0
STARTIE 0
ERRIE 0
RBFIE 0
TBEIE 0
General call address reception interrupt
NACK reception interrupt
STOP condition interrupt
START condition interrupt
Error detection interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
15 I 2 C (I2C)
Remarks
15-23