Block Diagram; Fig. 15-12-1 Port A Block Diagram (Pa7 To Pa0) - Panasonic MN103001G/F01K User Manual

15.12 Port A

15.12.1 Block Diagram

Fig. 15-12-1 shows a block diagram for port A.
Internal data bus
A7 to A0
Output enable
signal
A7(n=7)
to A0(n=0)
or
ADM7(n=7)
to ADM0(n=0)
PAOUT
PAnO
PADIR
PAnD
M
P
X
PAMD
PAM
PAPU
PAIN
PAnI

Fig. 15-12-1 Port A Block Diagram (PA7 to PA0)

M
P
X
P... Represents one bit of each register.
I/O Ports
PAn
(n=7,6,5,4,3,2,1,0)
15-53