A/D Converter
14.3 Block Diagram
AN0
AN1
AN2
AN3
ADTRG
Timer 2
underflow
Divider
IOCLK
14-4
512
256
128
Shift registers for states
A/D conversion
trigger
Comparator
Fig. 14-3-1 The Block Diagram of A/D Converter
64
32
16
8
ADnBUF
Data buffer
10 bit x 4 ch
Data buffer selection
ADCTR
For multiple-
channel
INC
conversion
A/D interrupt request
4
2
1
1
VREFH
Conversion
results
Results writing
Interrupt
generator