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When using handshaking mode (Memory control register 3B B3WM = 1)
Bit No.
Bit name
1
WM
2
BM
4
BW
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
Note: Handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4.
If (MCLK frequency/SYSCLK frequency) = 1 or 2, set B3WM = 0 in MEMCTR3B.
After the reset is released, block 3 is set as follows:
Address output end timing
RE negate timing
WE negate timing
RE/WE assert timing
Bus cycle start timing
Bus cycle end timing
AS assert timing
AS negate timing
The bus width is 16 bits, and synchronous fixed wait mode is set.
Description
Block 3 wait mode
Block 3 bus mode
Block 3 bus width
AS assert timing
AS negate timing
Set so that:
ASN
ASA
WE negate timing
3MCLK
29MCLK
29MCLK
3MCLK
0MCLK
31MCLK
1MCLK
3MCLK
Setting conditions
1: Handshaking mode
0: Synchronous mode (SYSCLK synchronization)
0: 8 bits
1: 16 bits
00: 0MCLK
11: 3MCLK
000: prohibited
001: 1MCLK
111: 7MCLK
00000: 0MCLK
11111: 31MCLK
Bus Controller (BC)
8-21
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