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16-bit Timers
Timer 10 compare/capture B register
Register symbol: TM10CB
Address:
x'340010D0
Purpose:
This is the timer 10 compare/capture B register.
Bit No.
15
14
Bit
TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10
name
CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
Reset
0
0
Access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
When this register is set as a compare register, an interrupt request is generated when TM10BC and TM10CB
match.
The timer 10 cycle can be set by clearing TM10BC when TM10BC matches TM10CB.
The cycle is the set value + 1.
When this register is set as a double-buffer compare register, data that is written to TM10CB is stored temporarily
in a buffer, so it is possible that after writing TM10CB, a read of TM10CB will still return the value that was
previously stored there.
The value set in the buffer is loaded into the compare register under the conditions described below. In any of these
cases, the value in TM10BC becomes x'0000.
(1)
When timer 10 is initialized
(2)
When an overflow occurs (while TM10CAE is set to "0")
(3)
When TM10BC matches TM10CA (while TM10CA is set as a compare register, and TM10CAE is
set to "1".)
(4)
When capturing a value in TM10CA (while TM10CA is set as a capture register, and TM10CAE is
set to "1".)
When this register is set as a capture register, the value in TM10BC is captured in TM10CB and an interrupt request
is generated when the edge that was selected by the TM10BEG flag is input to the TM10IOB pin.
When this register is set as a dual-edge capture register, the value in TM10BC is captured in TM10CB and an
interrupt request is generated at either a rising edge or a falling edge.
11-16
13
12
11
10
0
0
0
0
9
8
7
6
5
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
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