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P.12-5
(In the table of Example.)
When CKSEL is "H" and oscillation frequency is 15 MHz
(or when CKSEL is "L" and oscillating frequency is 30 MHz)
P.12-7
(The 2nd line from the bottom.)
An oscillation stabilization wait time of at least 17ms is
recommended.
P.12-8
(In fig.12-5-2.)
4.369 ms to 1118.481 ms
P.13-43
Bit No.
7
6
Bit
SC3
SC3
TXF
RXF
name
Reset
0
Access
R
R
*1 Indicates the status of the external pin IRQ7
P.13-43
Chapter
(Following words in page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,
1,
13-36, 13-45, 13-46, 13-47.)
Chapter
transfer speed
13
transfer rate
baud rate
Chapter
(Following unit in page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,
1,
13-36, 13-46, 13-47.)
Chapter
bps
13
P.14-3
• Conversion accuracy
P.15-47
[Note 2]
When pin Nos. 48 to 45, respectively, are ...
P.16-8
(In the table 16-6-1.) Flash on-board write control register
P.16-8
(Name of FAREG in the table 16-6-1.) Flash address register
P.16-8
(Name of FAREGEX in the table 16-6-1.) Flash address register
P.16-8
(In the table 16-6-1.) Flash on-board write enable register
P.17-2
(From the 3rd line of [Ordering method 1].)
... for the user NMI processing routine. This is not necessary if NMIs
are not being used, however.)
P.17-2
(The 4th line of [Ordering method 2].)
...when an NMI ...
P.17-2
(The 6th line of [Ordering method 2].)
... of the user NMI processing routine ...
P.17-2
(The 7th line of [Ordering method 2].)
If the user is not using NMI processing, ...
P.17-3
(In the fig.17-2-2.) the NMI processing routine
Source
Destination
Appendix-
PUTX
Dm
PUTCX
10
GETX
GETCHX
GETCLX
MCST
Dm
MCST9
-
Errors
Overflow cycle
5
4
3
2
1
SC3
SC3
SC3
SC3
SC3
TBF
RBF
CTS
FEF
PEF
0
0
0
*1
0
0
R
R
R
R
R
10 bits 4 LSB (Linearity error)
Format
Code length
Execution Cycle
D0
2
D0
2
Dn
D0
2
D0
2
D0
2
Dn
D0
2
Dn
D0
2
Page
P.12-5
(In the table of Example.)
When CKSEL is "H" and oscillation frequency is 15 MHz
P.12-7
(The 2nd line from the bottom.)
An oscillation stabilization wait time of at least 14 ms is recommended.
P.12-8
(In fig.12-5-2.)
4.369 ms to 1118.481 ms <Recommended value is 14 ms or longer.>
P.13-43
Bit No.
0
Bit
SC3
OEF
name
Reset
0
Access
R
P.13-43
(Addition of the following note in the description of Bit No.3.)
Note: When P83A of the port 8 analog/digital input control register
P8AD is "1", IRQ7 is treated as "L" internally by the
microcontroller and reading the SC3CTS bit returns a value of
"0", regardless of the actual values of the port pins.
Chapter
(In page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,
1,
13-36, 13-45, 13-46, 13-47.)
Chapter
13
bit rate
Chapter
(In page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,
1,
13-36, 13-46, 13-47.)
Chapter
bit/s
13
P.14-3
• Conversion accuracy
P.15-47
[Note 2]
When pin Nos. 45 to 48, respectively, are ...
P.16-8
(In the table 16-6-1.) Flash on-board rewrite control register
P.16-8
(Name of FAREG in the table 16-6-1.) Flash address register (Lower)
P.16-8
(Name of FAREGEX in the table 16-6-1.) Flash address register (Upper)
P.16-8
(In the table 16-6-1.) Flash on-board rewrite enable register
P.17-2
(From the 3rd line of [Ordering method 1].)
... for the user non-maskable interrupt processing routine. This is not
necessary if non-maskable interrupts are not being used, however.)
P.17-2
(The 4th line of [Ordering method 2].)
...when a non-maskable interrupt ...
P.17-2
(The 6th line of [Ordering method 2].)
... of the user non-maskable interrupt processing routine ...
P.17-2
(The 8th line of [Ordering method 2].)
If the user is not using non-maskable interrupt processing, ...
P.17-3
(In the fig.17-2-2.) the non-maskable interrupt processing routine
Appendix-
PUTX
2
2
PUTCX
10
2
GETX
GETCHX
2
GETCLX
2
MCST
2
2
MCST
MCST9
-
(In addition to these corrections, how to describe the unit is changed ,
but the data are not changed.
Example) P.12-2, 2nd line of "12.2 Features"
Error : 8 to 15 MHz
- vii -
- vii -
Corrections
Overflow cycle
7
6
5
4
3
SC3
SC3
SC3
SC3
SC3
TXF
RXF
TBF
RBF
CTS
0
0
0
0
0
R
R
R
R
R
10 bits 5 LSB (Linearity error)
Source
Destination
Format
Code length
Dm
D0
Dm
Dn
D0
Dn
D0
Dn
D0
Dn
D0
Dm
Dn
D0
imm8
Dn
D0
Dn
D0
Correction : 8 MHz to 18 MHz )
2
1
0
SC3
SC3
SC3
FEF
PEF
OEF
0
0
0
R
R
R
Execution Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
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