Fig. 8-14-7 Dram Refresh Operation; Fig. 8-14-8 Dram Refresh Timing - Panasonic MN103001G/F01K User Manual

Refresh count value
REFC
Count interval
Refresh is executed
during idle cycle
REFE bit is set
MCLK
SYSCLK
An
RAS1
RAS2
ASR
CAS
"H"
RE
"H"
WEn
"Hi-Z"
Dn
For details on the ASR and RP settings, refer to the explanations in section 8.6.2, "Memory Block 1 Control
Register," and section 8.6.3, "Memory Block 2 Control Register."
For details on the RERS setting, refer to the explanation in section 8.6.5, "DRAM Control Register."
Note: When using blocks 1 and 2 as DRAM space simultaneously, the timing (ASR, RP) set in memory control
register 1A/B is used as the refresh timing for both block 1 and block 2.
0 REFC
Refresh is executed with
highest priority

Fig. 8-14-7 DRAM Refresh Operation

RERS
RP
Refresh

Fig. 8-14-8 DRAM Refresh Timing

0 REFC
Count interval
ASR
Bus Controller (BC)
8-69