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Watchdog timer control register
Register symbol: WDCTR
Address:
x'34004008
Purpose:
This register sets the watchdog timer operation control conditions.
Bit No.
7
6
Bit
WD
WD
name
CNE RST OVT OVF
Reset
0
0
Access
R/W R/W R/W
Bit No.
Bit name
0
WDCK0
1
WDCK1
2
WDCK2
(n + WDCK x 2)
Overflow cycle = 2
Where, n = 16 (CKSEL pin is "H") or n = 17 (CKSEL pin is "L");
WDCK = WDCK[2:0]; f: Oscillation input frequency [unit: MHz]
5
4
3
2
WD
WD
WD
-
CK2 CK1 CK0
0
0
0
0
R
R
R/W R/W R/W
Description
Clock source selection (LSB)
Clock source selection
Clock source selection (MSB)
These bits select the clock source for the high-order 8 bits of the counter.
When the reset state is released, the clock source corresponding to "001"
below is selected.
When CKSEL is "H"
000: 1/2
8
of the OSCI input
001: 1/2
10
010: 1/2
12
011: 1/2
14
100: 1/2
16
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
/(f x 10
) [ms]
Example
Selection
000
001
010
011
100
1
0
WD
WD
0
1
When CKSEL is "L"
of the OSCI input
of the OSCI input
of the OSCI input
of the OSCI input
Overflow cycle
When CKSEL is "H" and oscillating frequency is 15 MHz
Watchdog Timer
1/2
9
1/2
11
1/2
13
1/2
15
1/2
17
4.369 ms
17.476 ms
69.905 ms
279.620 ms
1118.481 ms
12-5
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