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P.6-3
Input frequency range
8 fosci 15 MHz
8 fosci 30 MHz
P.6-3
When the reset state is released, SYSCLK, MCLK, and IOCLK are
supplied starting after a certain oscillation stabilization wait time.
Note: • When a clock is supplied from external, input the clock to
the OSCI pin, and leave the OSCO pin open.
• For details on the oscillation stabilization wait time, refer to
Chapter 12, "Watchdog Timer."
P.6-4
fosci(MHz)
Multiple
fsys(MHz)
8 fosci 15
1
8 fsys 15
8 fosci 30
1/2
4 fsys 15
P.8-5
Oscillator input pin (when using PLL: 8MHz to 15MHz; when
not using PLL: 8MHz to 30MHz)
Oscillator output pin (when using PLL: 8MHz to 15MHz; when
not using PLL: 8MHz to 30MHz)
P.8-11,
P.8-15
P.8-15,
(The Setting condition of EA1 to 0 bit in the table of "When Using
P.8-20
handshaking mode")
00: 0MCLK
11: 3MCLK
P.8-35
P.8-35
P.8-36
P.8-41
Errors
PLL
When using
When not using
Frequency
Multiple
Frequency
Multiple
fc (MHz)
32 fc 60 *
4
1
2
16 fc 30
1/2
1
8 fc 15
1/4
1/2
4 fc 15
1/8
Function
Page
P.6-3
Input frequency range
8 MHz fosci 18 MHz
8 MHz fosci 20 MHz
P.6-3
When the reset state is released, SYSCLK, MCLK, and IOCLK are
supplied starting after a certain oscillation stabilization wait time.
Note: For details on the oscillation stabilization wait time, refer to
Chapter 12, "Watchdog Timer."
Note 1: When a clock is supplied from external, input the clock to the
OSCI pin, and leave the OSCO pin open.
Note 2: The in-circuit emulator (ICE) cannot operate with self-excited
oscillators in the microcontroller. Use the clock generated in the
target system.
When the clock is generated in the target system, supply the
clock to the in-circuit emulator main unit through a buffer with
adequate drive capability. The in-circuit emulator will not operate
correctly if the amplitude of the clock is inadequate, the clock
signal is noisy, or the buffer has inadequate drive capability.
P.6-4
fosci(MHz)
Frequency
fio (MHz)
8 fio 15
8 fosci 15
4 fio 7.5
8 fosci 18
2 fio 3.75
1 fio 3.75
8 fosci 20
P.8-5
Oscillator input pin (when using PLL: 8 MHz to 18 MHz; when
not using PLL: 8 MHz to 20 MHz)
Oscillator output pin (when using PLL: 8 MHz to 18 MHz; when
not using PLL: 8 MHz to 20 MHz)
P.8-11,
(Following note is added under the table of "When Using DRAM")
P.8-15
Note: When performing ICE trace/emulation in software page
mode, set the CAS parameter to a value of "5" or higher.
P.8-15,
(The Setting conditions of EA1 to 0 bit in the table of "When Using
P.8-20
handshaking mode")
00:
01:
10:
11:
P.8-35
(Following sentence is added to 13th line.)
_____
The DK signal connected to the microcontroller should be input so
as to be asserted from point EA+DW onward, and is negated before
the next access.
P.8-35
(In figure 8-13-4, the DK signal asserted by the read access was
changed so as to be negated before the write access. )
P.8-36
(In figure 8-13-5 and 8-13-6, the DK signal asserted by the read
access was changed so as to be negated before the write access.
Moreover, the signal name, CSn was changed to CS2. )
P.8-41
(Following sentence is added to 20th line.)
_____
The DK signal connected to the microcontroller should be input so
as to be asserted from point EA+DW onward, and is negated before
the next access.
- iv -
Corrections
When using
When not using
Multiple
Frequency
Multiple
Frequency
fsys(MHz)
fc (MHz)
32 fc 60 *
1
8 fsys 15
4
2
16 fc 36
1
8 fsys 18
1
8 fc 18
1/2
4 fsys 10
1/2
4 fc 10
Function
prohibited
1MCLK
2MCLK
3MCLK
____
____
____
PLL
Multiple
Frequency
fio (MHz)
1
8 fio 15
1/2
4 fio 9
1/4
2 fio 4.5
1/8
1 fio 2.5
____
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