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CPU
2.1 Basic Specifications of CPU
• Structure
• Instructions
• Basic performance
• Pipeline
• Address space
1
*
in the case of the MN103001G.
2
*
in the case of the MN1030F01K.
2-2
Load/store architecture
Data/Address/SP Registers x 9
(Data registers: 32-bit x 4, Address registers: 32-bit x 4, SP: 32-bit x 1)
Other Registers
(PC: 32-bit x 1, PSW: 16-bit x 1, Multiply/divide register: 32-bit x 1,
Branch target registers: 32-bit x 2)
Number of instructions
Number of addressing modes
Basic instruction length
Code assignment
Maximum internal operating
frequency
Minimum instruction execution
cycle
Register-register operations
Load/store
Conditional branch
5-stage (Instruction fetch, decode, execute, memory access, write-back)
4 GB
Unified space for instructions and data
(Instructions can not be read from internal data RAM.)
: 46
: 6
: 1 byte
: 1 byte to 2 bytes (basic part)
+ 0 byte to 6 bytes (extension)
: 60 MHz*
1
(external oscillation: 15 MHz)
40 MHz*
2
(external oscillation: 10 MHz)
: 1 cycle (16.7 ns*
1
/25 ns*
: 1 cycle
: 1 cycle
: 1 cycle to 3 cycles
2
)
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