Fig. 2-5-7 Stack Frame Configuration - Panasonic MN103001G/F01K User Manual

CPU
[Stack Frame]
When an interrupt is accepted, a stack frame is allocated and the total 6 bytes of information in the PC and PSW are
saved in order to return from the interrupt. However, since the transfer of data across the 32-bit boundary is prohibited,
the SP value must constantly be set to a multiple of 4. Accordingly, a stack frame is allocated as shown in
Fig. 2-5-7 so that the SP value is constantly set to a multiple of 4. Ultimately, an 8-byte area with a total of 6 bytes
of information is saved.
Smaller addresses
2-22
+3 +2 +1 4n
(Rsv.)
PSW
PC (Return address)

Fig. 2-5-7 Stack Frame Configuration

SP (After the interrupt)
SP (Before the interrupt)