Panasonic MN103001G/F01K User Manual page 11

5. Operating Mode
5.1 Overview ........................................................................................................................ 5-2
5.2 Reset Mode .................................................................................................................... 5-3
5.3 Low Power Mode ........................................................................................................... 5-4
6. Clock Generator
6.1 Overview ........................................................................................................................ 6-2
6.2 Features .......................................................................................................................... 6-2
6.3 Block Diagram ............................................................................................................... 6-2
6.4 Description of Operation ................................................................................................ 6-3
6.4.1
6.4.2
7. Internal Memory
7.1 Overview ........................................................................................................................ 7-2
7.2 Features .......................................................................................................................... 7-2
7.3 Internal Memory Configuration ..................................................................................... 7-3
8. Bus Controller (BC)
8.1 Overview ........................................................................................................................ 8-2
8.2 Features .......................................................................................................................... 8-2
8.3 Bus Configuration .......................................................................................................... 8-3
8.4 Block Diagram ............................................................................................................... 8-3
8.5 Pin Functions ................................................................................................................. 8-5
8.6 Description of Registers ................................................................................................. 8-7
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.7 Space Partitioning ........................................................................................................ 8-26
8.8 Operation Clocks ......................................................................................................... 8-28
8.9 Mode Settings .............................................................................................................. 8-28
8.10 Bus Cycle ..................................................................................................................... 8-29
8.11 Store Buffer .................................................................................................................. 8-30
8.12 Accessing the Internal I/O Space ................................................................................. 8-31
8.13 External Memory Space Access
8.13.1
Input Frequency Setting ................................................................................ 6-3
Internal Clock Supply ................................................................................... 6-3
Memory Block 0 Control Register ................................................................ 8-8
Memory Block 1 Control Register .............................................................. 8-10
Memory Block 2 Control Register .............................................................. 8-14
Memory Block 3 Control Register .............................................................. 8-19
DRAM control register ............................................................................... 8-22
Refresh count register ................................................................................. 8-23
Page Row Address Register ........................................................................ 8-24
Clock Control Register ............................................................................... 8-24
(Non-DRAM Spaces) .................................................................................... 8-32
16-bit Bus with Fixed Wait States, in Synchronous Mode
and in Address/Data Separate Mode ........................................................... 8-33
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