Fig. 11-7-4 Event Count Operation - Panasonic MN103001G/F01K User Manual

[Note]
The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK
cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively.
Also note that event counting is not possible when IOCLK is stopped (in HALT or STOP mode).
IOCLK
Pin input
(TMnIO)
Count clock
TMnBC value x'0001
Interrupt request
signal (TMnIRQ)
x'0000

Fig. 11-7-4 Event Count Operation

TMnBR value
16-bit Timers
TMnBR value -1
11-37