Fig. 8-13-18 Access Timing On A 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 2); Fig. 8-13-19 Access Timing On A 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk) - Panasonic MN103001G/F01K User Manual

MCLK
SYSCLK
BCS
A23* to 16
ADM15 to 0
CSn
AS
RWSEL
RE
WEn
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
MCLK
SYSCLK
BCS=0
A23* to 16
ADM15 to 0
CSn
AS
RWSEL
RE
WEn
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
Fig. 8-13-19 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
BCE BCS
addr
"0"( "L" )
addr
data in
ADE
ASA
ASN
EA
REN
Read
BCE BCS=0
addr "0"( "L" )
addr
data in
ADE
ASA
ASN
EA
REN
Read
BCE
addr
"0"( "L" )
data out
addr
ADE
ASA
ASN
WEN
EA
Write
BCE
addr "0"( "L" )
addr data out
ADE
ASA
ASN
WEN
EA
Write
Bus Controller (BC)
8-47