Memory Block 2 Control Register - Panasonic MN103001G/F01K User Manual

Bus Controller (BC)

8.6.3 Memory Block 2 Control Register

Memory control register 2A/B is used to set the memory block 2 read/write timing, synchronous/asynchronous
mode, fixed wait/handshaking mode, DRAM mode, page mode, and bus width through software.
Memory control register 2A
Register symbol: MEMCTR2A
Address: x'32000034
Purpose: Sets the access timing, etc., for external memory space block 2.
Bit No. 15 14
Bit B2 B2
name REN4 REN3 REN2 REN1 REN0 BCE4 BCE3 BCE2 BCE1 BCE0 ADE1 ADE0 EA1 EA0 BCS1 BCS0
Reset 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: For the external memory access timing charts, refer to section 8.13, "External Memory Space Access (Non-
DRAM Spaces)."
For the timing charts when using DRAM, refer to section 8.14, "External Memory Space Access (DRAM
Spaces)."
When using fixed wait mode and not using DRAM (Memory control register 2B B2DRAM = 0, B2WM = 0)
Bit No. Bit name
1 to 0 BCS1 to 0
3 to 2 EA1 to 0
5 to 4 ADE1 to 0
10 to 6 BCE4 to 0
15 to 11 REN4 to 0
Note: nfr = MCLK frequency/SYSCLK frequency
8-14
13 12 11 10
B2 B2 B2 B2
1 0 1 1
Bus cycle start timing
n
When fr = 2, settings other than "00" or "01" are prohibited.
n
When fr = 1, settings other than "00" are prohibited.
RE/WE assert timing
Address output end timing
Bus cycle end timing
Set so that:
BCE REN, BCE WEN
BCE ASN + ADE
RE negate timing
9 8 7 6
B2 B2 B2 B2
1 1 1 1
Description
EA
5 4 3 2
B2 B2 B2 B2
1 1 1 1
Setting conditions
00: 0MCLK
01: 1MCLK
10: 2MCLK
11: 3MCLK
00: 0MCLK
11: 3MCLK
00: 0MCLK
11: 3MCLK
Settings other than those
shown below are prohibited.
00100: 4MCLK
11111: 31MCLK
Settings other than those
shown below are prohibited
00100: 4MCLK
11111: 31MCLK
1 0
B2 B2
0 0
.