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Bus Controller (BC)
After the reset is released, block 2 is set as follows:
Address output end timing
RE negate timing
WE negate timing
RE/WE assert timing
Bus cycle start timing
Bus cycle end timing
AS assert timing
AS negate timing
The bus width is 16 bits, and synchronous fixed wait mode is set.
8-18
3MCLK
29MCLK
29MCLK
3MCLK
0MCLK
31MCLK
1MCLK
3MCLK
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