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Group 5 interrupt control register
Register symbol: G5ICR
Address:
x'34000114
Purpose:
This register is used to enable group 5 interrupts, and to confirm interrupt requests and detection.
Bit No.
15
14
Bit
-
G5
name
LV2 LV1 LV0
Reset
0
0
Access
R
R/W R/W R/W
Bit No.
Bit name
0
T10UID
1
T10AID
2
T10BID
3
—
4
T10UIR
5
T10AIR
6
T10BIR
7
—
8
T10UIE
9
T10AIE
10
T10BIE
11
—
12
G5LV0
13
G5LV1
14
G5LV2
15
—
13
12
11
10
G5
G5
-
T10B T10A T10U
IE
IE
0
0
0
0
R
R/W R/W R/W
Description
Timer 10 overflow interrupt detection flag
0: No interrupt detected
Timer 10 compare/capture A interrupt detection flag
0: No interrupt detected
Timer 10 compare/capture B interrupt detection flag
0: No interrupt detected
"0" is returned when this bit is read.
Timer 10 overflow interrupt request flag
0: No interrupt request
Timer 10 compare/capture A interrupt request flag
0: No interrupt request
Timer 10 compare/capture B interrupt request flag
0: No interrupt request
"0" is returned when this bit is read.
Timer 10 overflow interrupt enable flag
0: Disabled
Timer 10 compare/capture A interrupt enable flag
0: Disabled
Timer 10 compare/capture B interrupt enable flag
0: Disabled
"0" is returned when this bit is read.
Group 5 interrupt priority level register (LSB)
Group 5 interrupt priority level register
Group 5 interrupt priority level register (MSB)
Set a level from 6 to 0.
"0" is returned when this bit is read.
9
8
7
6
5
-
T10B T10A T10U
IE
IR
IR
0
0
0
0
0
R
R/W R/W R/W
1: Interrupt detected
1: Interrupt detected
1: Interrupt detected
1: Interrupt request
1: Interrupt request
1: Interrupt request
1: Enabled
1: Enabled
1: Enabled
Interrupt Controller
4
3
2
1
-
T10B T10A T10U
IR
ID
ID
ID
0
0
0
0
R
R/W R/W R/W
9-13
0
0
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