Dram; Fig. 8-14-5 Dram Page Mode Read/Write Timing - Panasonic MN103001G/F01K User Manual

8.14.2 DRAM page mode
If the PAGE bit in the DRAM control register is set to "1", page mode access is enabled, making high-speed access
in page mode possible for following accesses to DRAM.
(1) Word/half-word access when the bus width is set to 8 bits
(2) Word access when the bus width is set to 16 bits
Fig. 8-14-5 shows the page mode read timing and write timing.
MCLK
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
An
Row
CAO
ASR
RASn
CAS
RE
Dn
(a) Read Timing
MCLK
An
Row
CAO
ASR
RASn
CAS
WE n
Dn
(b) Write Timing

Fig. 8-14-5 DRAM Page Mode Read/Write Timing

olumn olumn
C C
ASC ASC
RSH
CAS CAS
olumn olumn
C C
ASC ASC
RSH
CAS CAS
Bus Controller (BC)
8-65