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Bus Controller (BC)
8.6.5 DRAM control register
DRAM control register
Register symbol: DRAMCTR
Address:
x'32000040
Purpose:
Stores various DRAM mode settings when DRAM is connected.
Bit No.
15
14
Bit
–
–
name
Reset
0
0
Access
R
R
Bit No.
Bit name
0
DRAME
1
PAGE
2
REFE
3
BWC
7 to 6
SIZE1 to 0
11 to 8
RERS3 to 0 Number of MCLK while RAS is asserted
For details on the RAS hold time, the RAS precharge cycle, the CAS pulse width, the row address setup timing, the
column address output timing, and the column address setup timing, refer to memory control registers 1A/B and
2A/B.
For the timing charts when using DRAM, refer to section 8.14, "External Memory Space Access (DRAM Spaces)."
8-22
13
12
11
10
RERS RERS RERS RERS SIZE SIZE
–
–
3
2
0
0
0
0
R
R
R/W R/W R/W R/W R/W R/W
Description
DRAM control circuit enable
Page mode enable
Refresh enable
Byte wide control
DRAM size
00: Shift the address 9-bits to the low-order side and use as the row address
01: Shift the address 10-bits to the low-order side and use as the row address
10: Shift the address 11-bits to the low-order side and use as the row address
11: Shift the address 8-bits to the low-order side and use as the row address
in the refresh cycle.
9
8
7
6
1
0
1
0
1
1
0
0
5
4
3
2
–
–
BWC REFE PAGE
0
0
0
0
R
R
R/W R/W R/W R/W
Setting conditions
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: 2 WE control
1: 2 CAS control
0000: prohibited
0001: 1MCLK
1111: 15MCLK
1
0
DRAM
E
0
0
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