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When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1)
Bit No.
Bit name
0
DRAM
1
WM
2
BM
3
PE
4
BW
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
When using DRAM (Memory control register 2B B2DRAM = 1 B2WM = 0)
Bit No.
Bit name
0
DRAM
1
WM
2
BM
3
PE
4
BW
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
Description
Block 2 DRAM
space setting
Block 2 wait mode
Block 2 bus mode
Block 2 software page
mode enable
Block 2 bus width
AS assert timing
AS negate timing
Set so that:
ASN
ASA
WE negate timing
Description
Block 2 DRAM
space setting
Block 2 wait mode
Block 2 bus mode
Block 2 software page
mode enable
Block 2 bus width
Always set 01
RAS precharge cycle
Use as parameter RP
WE negate timing
Set so that:
CAO (ADE) + CAS (REN) WEN
Setting conditions
0: Do not use as DRAM space.
1: Handshaking mode
0: Synchronous mode (SYSCLK synchronization)
Not using
0: 8 bits
1: 16 bits
00: 0MCLK
11: 3MCLK
000: prohibited
001: 1MCLK
111: 7MCLK
00000: 0MCLK
11111: 31MCLK
Setting conditions
1: Use as DRAM space
0: fixed wait mode
1: Asynchronous mode
(MCLK synchronization)
0: Disable
1: Enable
0: 8 bits
1: 16 bits
Settings other than 01 are prohibited.
000: prohibited
001: 1MCLK
111: 7MCLK
Settings other than those shown below are prohibited.
00100: 4MCLK
11111: 31MCLK
Bus Controller (BC)
8-17
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