Fig. 8-13-2 Access Timing On A 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 2); Fig. 8-13-3 Access Timing On A 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk) - Panasonic MN103001G/F01K User Manual

Bus Controller (BC)
MCLK
SYSCLK
BCS
An
CSn
RE
WEn
Dn
:Undefined
Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
MCLK
SYSCLK
An
CSn
RE
WEn
Dn
: Undefined
Fig. 8-13-3 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Separate Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
8-34
BCE
REN
EA
Read
BCS=0
BCE
REN
EA
Read
BCS BCE
WEN
EA
Write
BCS=0
BCE
WEN
EA
Write