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Bus Controller (BC)
8.1 Overview
The bus controller (BC) controls interfacing between the CPU core, internal I/O (peripherals), and devices external
to the chip. The bus controller also handles arbitration between the internal and external buses. In addition, in an
interface with devices external to the chip, it is possible to select whether address pins and data pins are separate or
multiplex. The bus controller outputs four chip select signals, RAS/CAS signals, and other signals for an external
bus interface, permitting ROM, SRAM, DRAM, and other peripheral LSIs to be connected directly to this
microcontroller.
8.2 Features
The features of the bus controller are described below.
High-speed control of the internal and external buses through the CPU clock (MCLK) is possible.
- Synchronous mode (synchronized with IOCLK) is supported for the internal I/O bus.
Synchronousmode (synchronized with SYSCLK) and asynchronous mode (synchronized with
MCLK) are supported for the external bus.
External memory space can be partitioned into four blocks
- Chip select signal output for each block
- The bus width can be set to 8 or 16 bits for blocks 0 to 3
- Blocks 0 to 3 can be switched between synchronous mode and asynchronous mode
- Blocks 0 to 3 permit the read/write timing to be set through the software
- Blocks 1 and 2 can be used as DRAM space
- Blocks 2 and 3 permit use for handshaking
DRAM interface
- Address multiplexing function
- Permit the read/write timing to be set through the software
- Support for software page mode through software settings
- Support for CAS-before-RAS refresh (Programmable refresh cycle)
Permits switching between separate/multiplex address and data pins through the external input pin
settings
- Blocks 0 to 3 permit switching between separate/multiplex address and data pins through the external
input pin settings
- Using multiplex address and data pins permit the allocation of microcontroller I/O and peripheral
pins and reducing the number of external device pins
- Permits direct connection with ROM, SRAM, and DRAM without external circuitry
Avoids time penalty during storage operations through use of store buffer (one word)
- Support for storage in on-chip peripheral circuits and external devices
- When the store buffer is empty, storage operations are completed with no wait states, and the CPU
can execute subsequent processing
8-2
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