MCLK
SYSCLK
An
CSn
RE
WEn
RASn
CAS
Dn
BR
BG
CPU
Fig. 8-15-1 Bus Arbitration Timing 1
(Bus Authority Release/Bus Authority Acquisition, nfr = 4)
MCLK
SYSCLK
An
CSn
RE
WEn
RASn
CAS
Dn
BR
BG
CPU
Fig. 8-15-2 Bus Arbitration Timing 2
(Bus Authority Release/Bus Authority Acquisition,
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
External device
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
External device
Bus access
Standby
Standby
Bus access
n
fr = 2)
Bus Controller (BC)
8-71