Fig. 8-13-14 Access Timing On A 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 2) - Panasonic MN103001G/F01K User Manual

MCLK
SYSCLK
An
CS2
RE
"H"
WE0
DK
D7-0
: Undefined
MCLK
SYSCLK
An
CS2
"H"
RE
WE0
DK
D7-0
: Undefined
Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
A[0]=0
BCE
Consumed internally
EA DW
by the BC
DK detection start
Read low-order side
(a) Read Timing
A[0]=0
BCE
Consumed internally
by the BC
EA
DW
DK detection start
WEN
Write low-order side
(b) Write Timing
A[0]=1
EA
DW
Consumed internally by the BC
DK detection start
REN
Read high-order side
A[0]=1
BCE
Consumed internally
by the BC
EA DW
DK detection start
WEN
Write high-order side
Bus Controller (BC)
BCE
REN
8-43