Table of Contents
Advertisement
Page
P.8-42
P.8-43
to
P.8-44
P.8-48
P.8-49
P.8-49
P.8-50
P.8-56
P.8-57
P.8-58
P.8-59
-
Errors
Page
P.8-42
(In figure 8-13-13 (a) and (b), the DK signal asserted by the low-
order side access was changed so as to be negated before the high-
order side access.)
P.8-43
(In figure 8-13-14 (a), (b) and figure 8-13-15 (a), (b), the DK signal
to
asserted by the low- order side access was changed so as to be
P.8-44
negated before the high-order side access. Moreover, the signal
____
name, CSn was changed to CS2. )
P.8-48
(Following sentence is added to 17th line.)
_____
The DK signal connected to the microcontroller should be input so
as to be asserted from point EA+DW onward, and is negated before
the next access.
P.8-49
(In figure 8-13-20, the DK signal was changed so as to be asserted
from point EA+DW onward. The DK signal asserted by the read
access was changed so as to be negated before the write access.)
P.8-49
(In figure 8-13-21, the DK signal was changed so as to be asserted
from point EA+DW onward. The DK signal asserted by the read
access was changed so as to be negated before the write access.
Moreover, the signal name, CSn was changed to CS2. )
P.8-50
(In figure 8-13-22, the DK signal asserted by the read access was
changed so as to be negated before the write access. Moreover,
____
the signal name, CSn was changed to CS2. )
P.8-56
(Following sentence is added to 23th line.)
_____
The DK signal connected to the microcontroller should be input so
as to be asserted from point EA+DW onward, and is negated before
the next access.
P.8-57
(In figure 8-13-27 (a) and (b), the DK signal asserted by the low-
order side access was changed so as to be negated before the high-
order side access. Moreover, the figure was changed to one in the
case that parameter values were EA=1 and DW=1.)
P.8-58
(In figure 8-13-28 (a) and (b), the DK signal was changed so as to
be asserted from point EA+DW onward.
____
The DK signal asserted by the low- order side access was changed
so as to be negated before the high-order side access. Moreover,
____
the signal name, CSn was changed to CS2. )
P.8-59
(In figure 8-13-29 (a) and (b), the DK signal asserted by the low-
order side access was changed so as to be negated before the high-
order side access. Moreover, the signal name, CSn was changed to
____
CS2. )
P.8-73
(Following two cautions are added.)
to
5. Interrupts are prohibited and the bus is locked (occupied by the
P.8-74
CPU) when executing BSET or BCLR, however, if a BSET or BCLR
instruction is executed during program execution in external memory,
a bus authority release due to an external bus request may be
interposed between the data read and data write by the BSET or
BCLR instruction.
If the atomic bus cycles (i.e. bus lock) of the BSET or BCLR
instruction need to be guaranteed in a system that uses multiple
processors, either of the following measures should be taken.
1. A program in which a BSET or BCLR instruction is executed
should be placed in internal memory.
2. Designate the bus authority request pin (BR) as a general-purpose
input port, and the bus authority release pin (BG) as a general-
purpose output port, for instance, so that bus requests cannot be
accepted during execution of a BSET or BCLR instruction.
- v -
Corrections
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
_____
_____
____
Advertisement
Table of Contents
