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MCLK
SYSCLK
A23* to 16
ADM15 to 0
RWSEL
WE0
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
MCLK
SYSCLK
A23* to 16
ADM15 to 0
CSn
RWSEL
WE0
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
Fig. 8-13-26 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
BCS=0
BCE
A[0]=0
A[0]=0
ADE
CSn
ASA
AS
ASN
RE
REN
"H"
Read low-order side
(a) Read Timing
BCS=0
BCE
A[0]=0
A[0]=0
ADE
ASA
AS
ASN
RE
"H"
WEN
EA
Write low-order side
(b) Write Timing
Address/Data Multiplex Mode (MCLK = SYSCLK)
BCE
"0" ("L")
A[0]=1
"0" ("L")
data in
data in
A[0]=1
ADE
ASA
ASN
EA
EA
REN
Read high-order side
BCE
"0"("L")
A[0]=1
"0"("L")
data out
data out
A[0]=1
ADE
ASA
ASN
WEN
EA
Write high-order side
Bus Controller (BC)
8-55
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