Fig. 8-13-22 Access Timing On A 16-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk) - Panasonic MN103001G/F01K User Manual

Bus Controller (BC)
MCLK
SYSCLK
A23* to 16
ADM15 to 0
CS2
ASA
AS
ASN
RWSEL
RE
WEn
DK
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
8-50
addr
"0"( "L" )
addr data in
ADE
BCE
Consumed internally
EA
DW
by the BC
DK detection start
Read
Address/Data Multiplex Mode (MCLK = SYSCLK)
addr
addr
ADE
ASA
ASN
EA
REN
Write
"0"( "L" )
data out
BCE
Consumed internally
DW
by the BC
DK detection start
WEN