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16-bit Timers
11.6.6 Interval Timer
When using timer 10 as an interval timer, make the settings according to the procedure described below.
This interval timer generates a compare/capture A interrupt request on the cycle that is set. (Refer to Figs. 11-6-11
to 11-6-14.)
The compare/capture B register can be used as a compare register or as a capture register.
Note: For details on the settings, refer to section 11.6.1, "Compare Register Settings," or section 11.6.2, "Capture
Register Settings."
Procedure for initiating operation
(1) Set the compare/capture A register mode.
Set the TM10MDA register as follows:
TM10AO2,1,0 Don't care
TM10ACE
TM10AEG
TM10AM1,0
(2) Set the timer division ratio.
Set the division ratio in TM10CA.
The compare/capture A interrupt cycle then becomes:
(value set in TM10CA + 1) x clock source cycle
(3) Set the operating mode.
Set the TM10MD register as described below:
TM10CK2,1,0 Don't care; Select any clock source.
TM10CAE
TM10ONE
TM10TGE
TM10PM1,0
TM10PME
TM10LDE
TM10CNE
When using 1/8IOCLK or 1/32IOCLK as the clock source, set TMPSCNE in the TMPSCNT register to
"1" to enable prescaler operation before enabling the counting operation for timer 10.
(4) Initialize the timer.
Set TM10LDE in the TM10MD register to "1" in order to initialize timer 10.
TM10BC is cleared, and the pin output is reset.
In addition, if TM10CA is set as a double-buffer compare register, the value in the buffer is loaded into
the compare register.
After initialization is completed, be certain to reset TM10LDE back to "0" in order to restore normal
operation mode.
(5) Set the I/O port (when using pin output).
Set the I/O port to "timer output pin."
In the I/O port register, select "timer output" for the output signal and then set the output pin.
For details on the I/O port register settings, refer to chapter 15, "I/O Ports."
(6) Enable the timer counting operation.
The counting operation starts when the TM10CNE in the TM10MD register is set to "1".
Once the counting operation is enabled, a compare/capture A interrupt request is generated on a regular cycle.
11-28
0: Capture operation disabled
Don't care
00: Compare register (single-buffer)
or
01: Compare register (double-buffer)
If the interrupt cycle will change while the counting operation is in progress, be certain
to set "double-buffer."
1:
Clears TM10BC when TM10CA matches TM10BC.
0:
Disables one-shot operation.
0:
Disables timer start by an external trigger.
Don't care; This setting is ignored.
0:
Selects the normal waveform.
0:
Normal operation.
0:
Stops counting operation.
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