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Watchdog Timer
3
—
4
WDOVF
5
WDOVT
6
WDRST
7
WDCNE
[Notes]
1.
When resetting the value of watchdog overflow by writing the WDRST flag, do not simultaneously
overwrite the WDOVT flag.
If this flag is overwritten, the value of watchdog overflow reset is not guaranteed.
2.
When changing the values of WDCK2 to 0, first stop the watchdog timer and reset the counter.
Reset control register
Register symbol: RSTCTR
Address:
x'34004004
Purpose:
This flag causes the program to generate an internal reset.
Bit No.
7
6
Bit
-
-
name
Reset
0
0
Access
R
R
Bit No.
Bit name
0
CHIPRST
12-6
When this bit is read, a "0" is returned.
The value of the watchdog timer overflow output.
Watchdog timer overflow output selection
0: Pulse output
1: Level output
Binary counter reset, watchdog timer overflow output (WDOVF flag) reset
0: No reset
1: Reset
When a "1" is written to this bit, the reset pulse is generated for the width of
one clock pulse, and then this bit returns to "0". "0" is returned whenever
this bit is read.
Watchdog timer count operation control flag
0: Count operation stopped
(oscillation stabilization wait operation is possible)
1: Count operation enabled
5
4
3
2
-
-
-
-
0
0
0
0
R
R
R
R
Description
This flag is used to generate a self-reset (an internal reset of the chip due to an
internal cause). A self-reset is generated when this flag is overwritten from "0" to
"1".
A self-reset is not generated if this flag is already set to "1" when it is written with
a "1".
The value stored in this flag is retained even after the reset.
The CHIPRST flag is cleared either by an external reset signal (RST) or by writing
a "0" to this flag through the software.
1
0
CHIP
-
RST
0
0
R
R/W
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