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Extension Instruction Specifications
MACU (Unsigned multiply-and-accumulate operation instruction: between registers)
[Instruction Format (Macro Name)]
MACU Dm, Dn
[Assembler Mnemonic]
udf29 Dm, Dn
[Operation]
This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension
function unit.
The instruction multiplies the contents of Dm (unsigned 32-bit integer: multiplicand) by the contents of Dn (unsigned
32-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the
upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and
it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower
32 bits in the multiply-and-accumulate register MCRL.
If an overflow from the 64-bit cumulative sum data is generated when the product is added to the cumulative sum,
multiply-and-accumulate overflow detection flag 1 is output to register MCVF.
[Flag Changes]
Flag
Change
V
–
C
–
N
–
Z
–
[Programming Cautions]
A non-extension instruction that consumes at least two cycles must be inserted between this instruction and the next
extension instruction.
3-18
Condition
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