Fig. 8-13-29 Access Timing On A 8-Bit Bus With Handshaking In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk) - Panasonic MN103001G/F01K User Manual

MCLK
SYSCLK
A23* to 16
ADM15 to 0
CS2
ASA
AS
ASN
RWSEL
RE
"H"
WE0
DK
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
MCLK
SYSCLK
A23* to 16
ADM15 to 0
CS2
ASA
AS
ASN
RWSEL
RE
"H"
WE0
DK
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
Fig. 8-13-29 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
A[0]=0
"0" ("L")
A[0]=0
ADE
BCE
Consumed internally
EA DW
by the BC
DK detection start
Read low-order side
(a) Read Timing
"0" ("L")
A[0]=0
A[0]=0
data out
ADE
BCE
Consumed internally
EA DW
by the BC
DK detection start
Write low-order side
(b) Write Timing
Data Multiplex Mode (MCLK = SYSCLK)
"0" ("L")
A[0]=1
data in A[0]=1
ADE
ASA
ASN
EA
REN
Read high-order side
A[0]=1
"0" ("L")
A[0]=1
ADE
ASA
ASN
EA
WEN
Write high-order side
Bus Controller (BC)
data in
BCE
Consumed internally
DW
by the BC
DK detection start
REN
data out
BCE
Consumed internally
DW
by the BC
DK detection start
WEN
8-59