Panasonic MN103001G/F01K User Manual page 43

CPU Mode Register (CPUM)
The CPU mode register (CPUM) sets the clock operating mode for the CPU and peripheral blocks. This register is
allocated to the internal I/O space at address x'20000040.
Bit No.
15 14
Bit name
— —
Reset
0 0
Access
R R
Bit No. Bit name
0 OSC0
1 OSC1
2 SLEEP
3 HALT
4 STOP
5 OSCID
15 to 6 —
The various operating modes can be set by setting the bits as shown in the table below.
Operating mode STOP HALT SLEEP OSC1 OSC0
NORMAL 0
HALT 0
SLEEP 0
STOP 1
The CPUM register should be accessed by halfwords (16 bits). Byte and word access is not supported.
If the CPUM register is accessed to make a transition to an operating mode of SLEEP/HALT/STOP during execution
of a program in external memory, a branch instruction should not be located within the three instructions immediately
following the CPUM register access instruction.
13 12 11 10 9
— — — — —
0 0 0 0 0
R R R R R
Description
Always returns "0" when read. Always write "0".
Always returns "0" when read. Always write "0".
CPU operating mode control flag (SLEEP transfer request)
CPU operating mode control flag (HALT transfer request)
CPU operating mode control flag (STOP transfer request)
Always returns "0" when read. Always write "0".
reserved
Oscillation control and operating mode control
0 0 0
1 0 0
0 1 0
0 0 0
8 7 6 5
— — —
OSCID STOP HALT SLEEP OSC1 OSC0
0 0 0 0
R R R R R/W
Clock CPU operation Peripheral function
oscillation clock
0 Oscillating Running
0 Oscillating Stopped
0 Oscillating Stopped
0 Stopped Stopped
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W
operation clock
Running
Stopped
Running
Stopped
CPU
2-9